Essential Terms in Advanced IC Packaging Technology

 Advanced IC packaging is evolving rapidly, design engineers and engineering managers must keep pace with this significant technology. Before seeking deeper into the packaging technology, it is important to know the fundamental terms that keep coming in advanced IC packaging.

•   2.5D packaging:

In 2.5D packages, dies are stacked side by side on top of an interposer supported through-silicon vias(TSV) . The base, an interposer, provides connectivity between the chips.The 2.5D packages enable finer lines and spaces which is an upgradation to traditional 2D IC packaging technology 

• 3D packaging:

In 3D IC packages, logic dies are stacked on one another or memory dies rather than creating an outsized system-on-chip (SoC), and dies are connected using a lively interposer. Unlike 2.5D IC packages that stack components on an interposer through conductive bumps or TSVs, a 3D IC package employs multiple layers of silicon wafers stalked together along side components using TSVs.

• Chiplets:

Chiplets are a menu of modular chips  integrated into a package using die-to-die interconnect during a library . They are another type of 3D IC packaging that enable heterogeneous integration of CMOS devices with non-CMOS devices. In other words, they're smaller SoCs, or chiplets, rather than one big SoC during a package.

• Fan out

Fan-out packages, during which connections are fanned out of the chip surface to facilitate more external I/Os, use an epoxy mold compound to completely embed the dies, in order that they don’t require process flows like wafer bumping, fluxing, flip-chip assembly, cleaning, underfill dispensing, and curing. That, in turn, eliminates the necessity for an interposer and makes the implementation of heterogeneous integration simpler.

• Fan-out wafer-level packaging (FOWLP)

  
  

An improvement over wafer-level packaging (WLP), this system has been developed to supply more external contacts with silicon die. It embeds chips inside the epoxy molding compound then fabricates high-density redistribution layers (RDLs) and solder balls on the wafer surface to make a reconstituted wafer.

• Heterogeneous integration

  
  

The integration of separately manufactured components into a higher-level assembly provides enhanced functionality and improved operating characteristics. It enables semiconductor device manufacturers to combine functional components from different manufacturing process flows into a single composite device.

• High bandwidth memory (HBM)

HBM is a standardized stacked memory technology which gives wide channels for data. The HBM-based packaging stacks memory dies on top of every other and connects them using TSVs to make more I/Os and bandwidth.

• Interposer

It’s a conduit utilized in multi-chip die or boards to undergo electrical signals during a package. An interposer is an electrical interface routing between one socket  to another; it either spreads the signal to a wider pitch or takes the connection to a special socket on the board.

• Redistribution layer (RDL)

Redistribution layers are copper metal connection lines or traces that electrically connect one a part of the package with another. RDLs are created with layers of metal or polymer dielectric materials to stack dies on a package and thus relieve the I/O pitch on large chipsets. 

• Through silicon via (TSV)

TSV is a technology in 2.5D and 3D packaging solutions. It provides a vertical interconnection that passes through a die’s silicon wafer. It’s manufactured in wafer form and is crammed with copper. TSV is an electrical connection through the whole thickness of the chip that makes the shortest possible path from one side of the chip to the opposite .

  

If  you want to know more about the advanced IC packaging  do check our blog  other blogs on Advanced IC Packaging.

•    https://shraddha-kshirsagar18.medium.com/advanced-ic-packaging-1d0bac47e190
•    https://riyakaktikar.blogspot.com/2020/12/advanced-ic-packaging-techniques.html
•    https://shahikirti24.medium.com/advanced-ic-packaging-requirements-challenges-and-solutions-20c9605108a6
• https://kumbhareruj2000.medium.com/recent-news-in-advanced-ic-packaging-techniques-da9a91d80c2

REFERENCES :

1. https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/chiplets/
2. https://anysilicon.com/choose-silicon-via-tsv-packaging-improved-performance/
3. https://www.sciencedirect.com/topics/engineering/interposer

AUTHOR:Ankita Karwankar

  

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